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Data Sheet
Note that the integrator has a ?20 dB/dec attenuation and
approximately ?90° phase shift. When combined with a di/dt
sensor, the resulting magnitude and phase response should be a
flat gain over the frequency band of interest. However, the di/dt
sensor has a 20 dB/dec gain associated with it and generates
significant high frequency noise. A more effective antialiasing
filter is needed to avoid noise due to aliasing (see the Theory of
Operation section).
When the digital integrator is switched off, the ADE7758 can be
used directly with a conventional current sensor, such as a
current transformer (CT) or a low resistance current shunt.
PEAK CURRENT DETECTION
The ADE7758 can be programmed to record the peak of the
current waveform and produce an interrupt if the current
exceeds a preset limit.
Peak Current Detection Using the PEAK Register
The peak absolute value of the current waveform within a fixed
number of half-line cycles is stored in the IPEAK register.
Figure 47 illustrates the timing behavior of the peak current
detection.
L2
ADE7758
Note that the number of half-line cycles is based on counting
the zero crossing of the voltage channel. The ZXSEL[2:0] bits in
the LCYCMODE register determine which voltage channels are
used for the zero-crossing detection. The same signal is also
used for line cycle energy accumulation mode if activated (see
the Line Cycle Accumulation Mode Register (0X17) section).
OVERCURRENT DETECTION INTERRUPT
Figure 48 illustrates the behavior of the overcurrent detection.
CURRENT PEAK WAVEFORM BEING MONITORED
(SELECTED BY PKIRQSEL[2:0] IN MMODE REGISTER)
IPINTLVL[7:0]
PKI RESET LOW
WHEN RSTATUS
REGISTER IS READ
PKI INTERRUPT FLAG
(BIT 15 OF STATUS
REGISTER)
READ RSTATUS
REGISTER
L1
Figure 48. ADE7758 Overcurrent Detection
CURRENT WAVEFORM
(PHASE SELECTED BY
PEAKSEL[2:0] IN
MMODE REGISTER)
NO. OF HALF
LINE CYCLES
SPECIFIED BY
LINECYC[15:0]
REGISTER
Note that the content of the IPINTLVL[7:0] register is
equivalent to Bit 14 to Bit 21 of the current waveform sample.
Therefore, setting this register to 0xA1 represents putting peak
detection at full-scale analog input. Figure 48 shows a current
exceeding a threshold. The overcurrent event is recorded by
setting the PKI flag (Bit 15) in the interrupt status register. If the
PKI enable bit is set to Logic 1 in the interrupt mask register, the
IRQ logic output goes active low (see the Interrupts section).
CONTENT OF
IPEAK[7:0]
00
L1
L2
L1
Similar to peak level detection, multiple phases can be activated
Figure 47. Peak Current Detection Using the IPEAK Register
Note that the content of the IPEAK register is equivalent to
Bit 14 to Bit 21 of the current waveform sample. At full-scale
analog input, the current waveform sample is 0x2851EC. The
IPEAK at full-scale input is therefore expected to be 0xA1.
for peak detection. If any of the active phases produce
waveform samples above the threshold, the PKI flag in the
interrupt status register is set. The phase of which overcurrent is
monitored is set by the PKIRQSEL[2:0] bits in the MMODE
register (see Table 19).
In addition, multiple phases can be activated for the peak
detection simultaneously by setting more than one of the
PEAKSEL[2:4] bits in the MMODE register to logic high. These
bits select the phase for both voltage and current peak
measurements. Note that if more than one bit is set, the VPEAK
and IPEAK registers can hold values from two different phases,
that is, the voltage and current peak are independently
processed (see the Peak Current Detection section).
Rev. E | Page 21 of 72
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